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1 of 13 rev: 113004 note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, click here: www.maxim-ic.com/errata . general description the DS21600/ds21602/ds21604 are multiple-rate clock adapters that convert between e-carrier and t- carrier clocks rates. a t1 or e1 clock output, clkout1, is available, along with a higher multiple rate clock output, clkout2. clkout1 and clkout2 are frequency locked to the clock input clkin. the clock outputs, along with frame-sync output, can be phase-aligned to a frame-sync input. the devices are fully compatible with the lxp600a, lxp602, and lxp604, and operate from either a 5v or 3.3v supply. all operation modes include a standard 8khz output. the DS21600/ds21602/ds21604 are available in 16-pin so, and are rated for industrial temperatures. ordering information part temp range pin-package DS21600 sn -40c to +85c 16 so DS21600n -40c to +85c 8 dip ds21602 sn -40c to +85c 16 so ds21602n -40c to +85c 8 dip ds21604 sn -40c to +85c 16 so ds21604n -40c to +85c 8 dip frequency conversions (mhz) part clkin cl kout1 clkout2 1.544 2.048 6.144 DS21600 2.048 1.544 6.176 1.544 2.048 8.192 ds21602 2.048 1.544 6.176 1.544 4.096 8.192 ds21604 4.096 1.544 6.176 features direct drop-in replacement for lxp600ase, lxp602se, and lxp604se converts e-carrier clock rates to t-carrier clock rates converts t-carrier clock rates to e-carrier clock rates 3.3v or 5v supply low jitter output multiple output clocks synchronized to input clock 8khz frequency-locked output for all operation modes no external components required 16-pin so and 8-pin dip industrial temperature range: -40c to +85c pin configuration DS21600/ds21602/ds21604 3.3v/5v clock rate adapte r www.maxim-ic.com dallas semiconductor DS21600/2/4 top view so .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 2 of 13 table of contents 1. pin description ................................................................................................................ ......3 1.1 p in n ame c ross -r eference to lxp60x ....................................................................................................3 2. function al descri ption ......................................................................................................4 2.1 m ode s elect ............................................................................................................................... .................4 2.2 f rame s ync i nput ............................................................................................................................... .........4 3. output jitter .................................................................................................................. ........4 3.1 j itter t ransfer ............................................................................................................................... ...........5 4. operating parameters .......................................................................................................7 5. package information ........................................................................................................11 6. revision history............................................................................................................... ...13 list of figures figure 1-1. block diagram...................................................................................................... ..............3 figure 3-1. nominal jitter transer fo r 2.048mhz to 1.544m hz conver sion ..........................................5 figure 3-2. nominal jitter transfer fo r 1.544mhz to 2.048m hz conver sion .........................................6 figure 4-1. DS21600/ds21602 high- to-low frequency conversion frame-sync alignm ent ...............8 figure 4-2. ds21604 high-to -low frequency conversion frame-sync alignment..............................9 figure 4-3. DS21600 low-to- high frequency conversion fr ame-sync a lignment ...............................9 figure 4-4. ds21602 low-to- high frequency conversion fr ame-sync a lignment .............................10 figure 4-5. ds21604 low-to- high frequency conversion fr ame-sync a lignment .............................10 list of tables table 1-a. pin description ..................................................................................................... ...............3 table 1-b. pin name cross-reference to lxp60x ...............................................................................3 table 2-a. frequency conversions (mhz) ......................................................................................... ...4 table 3-a. output jitter specifications........................................................................................ ..........4 .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 3 of 13 1. pin description table 1-a. pin description pin dip so name type function ? 1, 3, 6, 8, 10, 11, 13, 15 n.c. ? no connect 1 2 syncout output synchronization output. an 8khz output that can be synchronized to the clock outputs. 2 4 clkout2 output clock output 2. t1 or e1 carrier clock output referenced to clkin. 3 5 clkin input clock input. reference clock input. clkout1 and clkout2 will be referenced to this clock. 4 7 clkout1 output clock output 1. t1 or e1 carrier clock output referenced to clkin. 5 9 vss supply ground 6 12 sel input clock mode select. conversion mode select. 7 14 syncin input synchronization input. used to synchronize the clock outputs and syncout to clkin and syncin. syncin should be tied high or low when not in use. 8 16 v dd supply positive supply, 3.3v or 5v 5% 1.1 pin name cross-reference to lxp60x table 1-b. pin name cross-reference to lxp60x DS21600/ds21602 /ds21604 lxp600alxp602/ lxp604 function syncout fso synchronization pulse output clkout2 hfo clock 2 output clkin clki clock input clkout1 clko clock 1 output v ss gnd ground sel sel clock mode select syncin fsi synchronization pulse input n.c. n.c. no connect v dd v cc positive supply figure 1-1. block diagram analog pll output divider frame sync generator clkin sel syncin clkout2 clkout1 syncout feedback circuit dallas semiconductor DS21600/ds21602/ds21604 .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 4 of 13 2. functional description a clock input at clkin is converted to an alternate cloc k rate available on clkout1. a higher multiple-rate clock also is available on clkout2. additionally, an 8khz cloc k locked to clkin is always available at the syncout pin. the sel pin controls clock-rate conversion selection. 2.1 mode select the sel pin is used to select the operating frequencies. table 2-a shows the sel state for the various operating modes of the DS21600, ds21602, and ds21604. table 2-a. frequency conversions (mhz) part sel clkin clkout1 clkout2 0 1.544 2.048 6.144 DS21600 1 2.048 1.544 6.176 0 1.544 2.048 8.192 ds21602 1 2.048 1.544 6.176 0 1.544 4.096 8.192 ds21604 1 4.096 1.544 6.176 2.2 frame-sync input in all cases, clkout1 and clkout2 are frequency-locked to clkin. clkout1, clkout2, and syncout are phased-locked to syncin when syncin is asserted. the signal applied to syncin can be 8khz or some integer subrate such as 1khz, 2khz, or 4khz. phase synchronization occurs within a maximum of 50ms when syncin is 8khz. 3. output jitter table 3-a shows the output jitter specifications for 2.048mhz (or 4.096mhz) to 1.544mhz conversions (sel = 1) and 1.544mhz to 2.048mhz (or 4.096mhz) conversions (sel = 0). table 3-a. output jitter specifications clkin (mhz) clkout1 (mhz) frequency band specification value typ max units 20hz?100khz g.823 1.500 0.018 0.035 ui p-p 1.544 2.048 18khz?100khz g.823 0.200 0.012 0.025 ui p-p no bandlimiting tr62411 0.050 0.010 0.020 ui p-p 10hz?40khz tr62411 0.025 0.005 0.010 ui p-p 2.048 or 4.096 1.544 8khz?40khz tr62411 0.025 0.006 0.012 ui p-p .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 5 of 13 3.1 jitter transfer figure 3-1 and figure 3-2 show jitter transfer for 2.048mhz-to-1.544mhz conversions and vice versa. figure 3-1. nominal jitter transfer for 2.048mhz-to-1.544mhz conversion 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 10 20 30 40 50 60 70 80 jitter frequency (khz) jitter gain (ns/ns) note: the typical peak jitter gain of the DS21600/ds21602/ds21604 is about 1.6 for conversion from t1 to e1. the typical peak-jitter gain of the level one device is about 1.1. however, the jitter gain for the DS21600/ds21602/ds21604 peaks in the 4khz to 8khz range, whereas the peak jitter gain for the lxp6xx devices spans a greater frequency range (20khz to 40khz). .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 6 of 13 figure 3-2. nominal jitter transfer for 1.544mhz-to-2.048mhz conversion 0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 0 5 10 15 20 25 30 35 40 jitter frequency (khz) jitter gain (ns/ns) note: the typical peak jitter gain of the DS21600/ds21602/ds21604 is about 1.6 for conversion from t1 to e1. the typical peak-jitter gain of the level one device is about 1.1. however, the jitter gain for the DS21600/ds21602/ds21604 peaks in the 4khz to 8khz range, whereas the peak jitter gain for the lxp6xx devices spans a greater frequency range (20khz to 40khz). .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 7 of 13 4. operating parameters absolute maximum ratings voltage range on any pin relative to ground -1.0v to +6.0v operating temperature range for DS21600s n, ds21602sn, ds21604sn -40c to +85c storage temperature range -55c to +125c soldering temperature see ipc/jedec j-std-020 specification stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of t he specifications is not implied. exposure to absolute maximum rating condi tions for extended periods can affect device reliability. recommended dc operating conditions (t a = -40c to +85c) parameter symbol conditions min typ max units logic 1 v ih 2.0 5.5 v logic 0 v il -0.3 +0.8 v 3.3v 3.135 3.3 3.465 supply voltage v dd 5v 4.75 5 5.25 v dc characteristics (v dd = 3.3v/5v 5%, t a = -40c to +85c.) parameter symbol conditions min typ max units supply current i dd (note 1) 14 ma input leakage i il (note 2) -1.0 +1.0 a output leakage i lo 1.0 a output current (2.4v) i oh -1.0 ma output current (0.4v) i ol +4.0 ma note 1: 100pf load on all outputs. note 2: 0v < v in < v dd . .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 8 of 13 ac timing ( figure 4-1 , figure 4-2 , figure 4-3 , figure 4-4 , and figure 4-5 ) parameter symbol conditions min typ max units capture range on clkin (note 3) 10,000 ppm lock range on clkin (note 3) 10,000 ppm clkin duty cycle (note 3) 35 65 % syncin setup to clkin rising t su 46 ns syncin hold after clkin rising t hi 30 ns syncin pulse width t pw 76 clkin period ns 3.3v -15 0 +15 clkout1 delay from clkin rising t d 5v -15 0 +31 ns clkout1 duty cycle c d 49 51 % syncout delay from clkout2 t df -5 30 ns syncout pulse width t spw clkout 1 period ns clkout1 delay from clkout2 rising t dh -15 0 +15 ns 3.3v 60 rise/fall time on clkin, syncin (note 3) t rf 5v 40 ns 3.3v 60 rise/fall time on clkout, syncout, clkout2 (note 4) t rf 5v 40 ns note 3: guaranteed by design. note 4: 100pf load on clkout, syncout, clkout . figure 4-1. DS21600/ds21602 high-to-low frequency conversion frame-sync alignment t pw t d clkout2 ( 6.176mhz ) t df t dh t hi t su clkout1 ( 1.544mhz ) syncin clkin ( 2.048mhz ) syncout t spw .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 9 of 13 figure 4-2. ds21604 high-to-low frequency conversion frame-sync alignment figure 4-3. DS21600 low-to-high frequency conversion frame-sync alignment syncout t dh t d t pw t hi t su clkout1 ( 1.544mhz ) syncin clkin ( 4.096mhz ) t df clkout2 ( 6.176mhz ) t spw t spw t dh t df t d t pw t su clkout2 ( 6.144mhz ) syncout clkout1 (2.048mhz) syncin clkin (1.544mhz) t hi .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 10 of 13 figure 4-4. ds21602 low-to-high frequency conversion frame-sync alignment figure 4-5. ds21604 low-to-high frequency conversion frame-sync alignment t sp t dh t df t d t pw t su clkout2 ( 8.192mhz ) syncout clkout1 (2.048mhz) syncin clkin (1.544mhz) t hi t dh t spw t df t d t pw t su syncout clkout1 (4.096mhz) syncin clkin (1.544mhz) t hi clkout2 (8.192mhz ) .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 11 of 13 5. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/dallasp ackinfo .) 16-pin so, 0.300" body .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 12 of 13 8-pin dip (300 mil) .com .com .com .com
DS21600/ds21602/ds21604 3.3v/5v clock rate adapter 13 of 13 6. revision history revision description 082100 preliminary release 083100 added package specifications 090100 correct operating voltage range 011101 added mechanical drawing for dip package 092801 added jitter specifications and pin list for all packages; added timing diagrams 032002 updated jitter specifications 032803 added 3.3v operation specifications 113004 added the spec for soldering temperature in the absolute maximum ratings section. .com .com .com

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